Prior art computer system architectures typically assume that each process within the computer system has equal access to shared structures. However, access to shared structures is not equal when one or more processes access a structure via bus or other communications device and other processes access the structure locally. The processes that access the structure locally typically have a much lower cost in terms of latency and overhead than processes that access the same structure via a bus.
Costs in accessing structures across a bus are asymmetric in the sense that write operations can be performed more efficiently than read operations because the device writing data is not required to wait for a response from the device to which data is written. Read operations, however, require that the reading device either wait for data to be returned or halt activity to receive data from the device that is read. When bridges or other devices are involved in a read operation the cost becomes even greater because multiple devices are used in the communications path, which requires multiple access requests and grants.
What is needed is an architecture that passes messages to and from shared structures that takes advantage of the fact that write operations are more efficient that read operations.